Welcome, glad to see you are interested in creating your own custom component that can be rapidly assembled into your design.

Below is a full list of hardware and software prerequisites:
  • Xilinx ISE Design Suite, you will need your own copy to install to your workstation to have this capability.
  • Acquire the client_component_template git repo provided here Template Git Repo
  • Synthesizeable HDL of the RFNoC module you wish to compile. There are examples in the client_component_template/hdl/rfnoc/modules/[module name]/src/
  • An Ethernet connection to the USRP
  • RDA component creation binaries and executables. These can be found in either a Pybombs recipe or a debian package.

Before jumping headfirst into RDA component creation, some background and explanation is needed.

Our getting started page has some links that provide information on RFNoC, which you’ll want some familiarity with.

Here is the Ettus Research git repo with the fpga src code: FPGA refnoc-devel

All RFNoC blocks use standard I/O interfaces to communicate over an AXI bus inside the FPGA. These interfaces and other parameters are defined below:

  • The Xilinx ISE Design Suite. You will need to install this package on your workstation to have this capability.
  • Acquire the client_component_template git repository Template Git Repo
  • Synthesizeable HDL of the RFNoC module you wish to compile. There are examples in the client_component_template/hdl/rfnoc/modules folder.
  • An Ethernet connection, direct or indirect, between your host computer and to the USRP
  • A full insand tallation of the gr-rda Pybombs package containing the component creation executables and libraries. These can be found as either a Pybombs recipe or a Debian package.
  • Before jumping into the component creation, some background and explanation is needed first.

    Our getting started page has links that provide information on RFNoC, in which you’ll want to become familiar.

    Here is the Ettus Research git repository with the FPGA source code: FPGA refnoc-devel . An example RFNoC component is shown below:

    module noc_block_axi_fifo_loopback #( 
    parameter NOC_ID = 64'hF1F0_0000_0000_0000, //unique identifier for this type of block 
    parameter STR_SINK_FIFOSIZE = 11) 
     input bus_clk, //clock for the AXI packet handling bus between modules
     input bus_rst, //reset for the AXI packet handling bus between modules
     input ce_clk, //Computation Engine clock (unused in the current RDA design)
     input ce_rst, //Computation Engine reset (unused in the current RDA design)
     input  [63:0] i_tdata, // Input data packets 
     input  i_tlast, // last data of a packet
     input  i_tvalid, // valid data packet
     output i_tready, // informing axi bus this module is ready for data
     output [63:0] o_tdata, // Output data packets
     output o_tlast, // last data packet
     output o_tvalid, // valid data packet
     input  o_tready, // axi bus informing this module that it is ready data
     output [63:0] debug // generally not used by TFlow, when

    These are the interfaces expected by RFNoC and RDA. In addition to being the standard RFNoC interfaces for a given RFNoC module, these interfaces are expected in the RDA source code as the module interfaces, so do not deviate from these.

    To meet timing during Rapid Assembly at runtime, some modules may need registered inputs and outputs to meet timing. See the example design in client_component_template/hdl/rfnoc/modules/noc_block_axi_fifo_loopback_reg to see how that is done.

    The NOC_ID parameter in the HDL needs to be a unique HEX identifier for a given RFNoC module. See the Ettus Research fpga-src repo linked above for examples of the HEX identifier used in other blocks.

    Implementation steps:

    1. All HDL and NGC source for your module should be placed in client_component_template/hdl/rfnoc/modules/[module_name]/src/
    2. Source the Xilinx Tools using the settings64.sh script. Source your Pybombs setup_env.sh script.
    3. WATCH OUT! Sourcing the Xilinx Tools sets your LD_LIBRARY_PATH which is known to cause conflicts other things that set your environment variables, including Pybombs.
    4. Navigate to the client_component_public_template repo directory and run:
    5. make -f Makefile_Module TOP="module_name" KEYFILE="path_to_keyfile.conf"
        You can also edit the Variables inside that Makefile, they are listed below. There are some other options in that Makefile as well such as:
        HDL_DIR : The HDL directory by default set for the rfnoc hdl directory, ./hdl/rfnoc/modules
        RDA_DIR : The RDA compiled module library and metadata directory by default is set for, ./modules/
        CLB_TOLERANCE, BRAM_TOLERANCE, DSP_TOLERANCE, & EXTRA_RESOURCE : Adjusts the size area allocation of a RDA module. RDA allocates an area for a module and does resource estimation to determine that area using Xilinx PlanAhead. Occasionally it underestimates or does not account for the routing resources properly. If routing takes an extra long time or mapping actual FPGA resources fails, then this option can be set to some whole value greater than 0 which represents the percentage more area to be allocated. By default these tolerances and extra resource amounts have been set to things that work best for us at Consolidated Logic.
        CLK : clock line in the module, default "bus_clk ce_clk", since RFNoC blocks have two clock lines (though we currently only use 1, bus_clk). If the clock line for the module has a different name, then mark that here.
        NUM_SHAPES : defaults to 10. Internal variable used, if you know what you're doing feel free to edit this, but 10 is recommended.
        SYNTH_LOG : name of the log captured for the first stage of compilation, synthesis
        MODULE_LOG : name of the log captured for the main phase of module component creation
        MAKEFILE_MODULE_LOG : location of the logging application
        LOG_BACKUP : backup of the most recent log. be sure to change this for each run so you don't automatically delete your most recent log backup.
    6. If the above Makefile script was successful, than congradulations, your module has been generated and registered with the cloud tool with your user. Look at this screenshot!

      • Output log GUI displayed after a sucessful local component creation, after this pops up, there's still a bit more. That happens, registering the component metadata in the local and cloud app cache.
    7. Add the module to UHD as seen here: Host Code C/C++ Block Control
        Public header: {PYBOMBS_ROOT}/pybombs/src/uhd/host/include/uhd/usrp/rfnoc/ Follow the examples there, e.g. fft_block_ctrl.hpp
        Implementation: {PYBOMBS_ROOT}/pybombs/src/uhd/host/lib/usrp/rfnoc/ e.g. fft_block_ctrl_impl.cpp
        XML descriptor: {PYBOMBS_ROOT}/pybombs/src/uhd/host/include/uhd/usrp/rfnoc/blocks e.g. fft.xml
        NOTE: Be sure to add these files to their appropriate CMake files as well. In the same directory as the files, add the file to whatever list of like-files exists in the CMake fle.
    8. Remake UHD, using pybombs {PYBOMBS_ROOT}/pybombs/pybombs install uhd
    9. Add the module to the gr-ettus block library
    10. Remake gr-ettus, using pybombs {PYBOMBS_ROOT}/pybombs/pybombs install gr-ettus
    11. Add the module to the gr-rda block dictionary. There is an automated script installed by pybombs that will do this for you, just run:
      • add_greasy_module [blockname] [modulename]
        [blockname] - RFNoC blockname ID that matches the blockname tag in the UHD XML. This is defined by the user when writing the UHD XML file and appears to be arbitrary.
        [modulename] - name of the top HDL of this module
    12. Remake gr-rda, using pybombs {PYBOMBS_ROOT}/pybombs/pybombs install gr-rda
    13. That's it, you're done. Your RFNoC block is ready to use in GNU Radio, rapidly assembled by the RDA cloud application.
    14. THIS TUTORIAL IS A WORK IN PROGRESS. If you have any further questions or something doesn't appear complete, contact our support.

    Consolidated Logic has multiple tutorials available to ease the setup and your introduction to RDA. These are links are available here:

    Don’t forget to create an account on our website to use RDA as a cloud application!

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